Samsung Electronics used last week's Hot Chips conference to detail a memory chip that does something conventional DRAM does not: perform computation inside the memory itself, rather than shuttling data back and forth to a separate processor. The part, called LPDDR5X-PIM, embeds processing-in-memory logic into a standard mobile memory package, and Samsung's own benchmarks show it roughly tripling AI inference throughput compared with ordinary LPDDR5X.
In testing that Samsung presented on August 25 and detailed by Tom's Hardware, running Meta's Llama 3.1 model produced 81.3 tokens per second on LPDDR5X-PIM versus 27.0 tokens per second on standard LPDDR5X — a 3.01x gain — while completion time for a fixed workload fell from 12.3 seconds to 5.4 seconds. The chip reaches 614 GB/s of processing-in-memory bandwidth, roughly eight times the 76.8 GB/s available through the conventional DRAM interface on the same part. Sixteen processing blocks, each combining a multiply-accumulate array with logic that handles both integer and floating-point math, sit inside the memory arrays themselves, so a portion of a model's matrix math runs where the weights already reside instead of crossing the memory bus first.
Aimed below the HBM price tier
The chip ships in a standard JEDEC 561-ball package with 16 GB spread across four dies, meaning it can be adopted without the specialized packaging that high-bandwidth memory requires. That is deliberate positioning: Samsung is pitching LPDDR5X-PIM as a lower-cost, lower-power option for AI inference in smartphones, AI-equipped PCs and edge accelerators — devices where HBM's cost, power draw and packaging complexity have made it a non-starter, according to a summary from ServeTheHome. Samsung says it is making a simulator, datasheet and software development kit available to partners evaluating the part.
The announcement was part of a broader push by Samsung's memory division to address what has become the central bottleneck in AI hardware: not raw compute, but how fast data can move between memory and processors. Earlier this month at the Future of Memory and Storage conference, the company also showed zHBM, an architecture that stacks high-bandwidth memory directly on top of an AI accelerator rather than beside it, and a new V10 bonded NAND design with more than 400 layers that Samsung says increases storage density by roughly 58% over its prior generation. Both received the conference's Best of Show award.
None of these are products consumers will encounter directly, and Samsung has not given a firm production timeline for LPDDR5X-PIM. But the approach reflects a shift underway across the memory industry: as HBM supply gets absorbed by the largest AI data-center buyers, chipmakers are racing to bring similar efficiency gains to the far larger volume of devices that will never touch an Nvidia GPU.
